As depicted in FIG. 1, a digital phase lock loop (DPLL) 100 comprises: a TDC (time-to-digital converter) 110 for receiving a reference clock and a feedback clock and outputting a timing error signal representing a difference in timing between the reference clock and the feedback clock; a digital loop filter 120 for receiving the timing error signal and outputting a control code by filtering the timing error signal; a DCO (digitally controlled oscillator) 130 for receiving the control code and outputting an output clock of an oscillation frequency controlled by the control code; and a divide-by-N circuit 140 for receiving the output clock and outputting the feedback clock by dividing down the output clock by a factor of N, where N is an integer. When the reference clock is faster than the feedback clock: the timing error signal is positive, causing the control code to increase, resulting in an increased frequency of the output clock, and accordingly the feedback clock. When the reference clock is slower than the feedback clock: the timing error signal is negative, causing the control code to decrease, resulting in a decrease of the output clock, and accordingly the feedback clock. Therefore, a timing of the output clock is controlled in a closed-loop manner so as to make a timing of the feedback clock track a timing of the reference clock.
TDC 110 is an important functional block in digital phase lock loop 100. For the feedback clock to be able to precisely track the reference clock, TDC 110 must have a high precision. TDC 110 quantizes the timing difference between the reference clock and the feedback clock into a digital word representing the timing error signal; the precision is determined by the weight of the LSB (least significant bit) of the digital word. Prior art TDC is usually constructed from a cascade of a plurality of unit delay cells, and the weight of the LSB is determined by a delay of the unit delay cell. In modern CMOS (complementary metal-oxide semiconductor) technologies, the delay of the unit delay cell is typically around 10 ps. Therefore, the precision of timing detection is limited to 10 ps. Although many efforts have been taken to seek to improve the precision of TDC, it is difficult to attain high precision without paying a high premium in circuit area and power consumption.
What is desired is a method of high precision timing detection for digital phase lock loop without using time-to-digital converter.